In the IBM ES/3090 Processor Complex is a PR/SM machine having an LPAR hypervisor. PR/SM refers to the machine hardware facility which allows the resources of a single physical system to be divided between distinct, predefined logical machines called "partitions." The separation and allocation of these physical resources is supported by the interpretive-execution facility of the machine and is performed by the hypervisor internal code called "LPAR". LPAR is a hypervisor or a virtual-machine monitor and in an overall system context can be referred to as the "host." Similarly, the individual partitions can be called "guest" machines.
In a PR/SM environment, some amount of contiguous host storage is made available to each of the logical partitions being managed by LPAR. Guest absolute storage is mapped into host absolute storage, and this segmentation and allocation of storage is accomplished by associating host storage "origin" and "limit" parameters for each logical partition. For each partition there is an origin value which designates where in host absolute storage that partition's storage begins, and a limit value that specifies where the partition's storage ends. As part of each guest storage reference, an origin value is added to the guest absolute address and the sum is then tested against the limit value to make sure that the referenced location is within the guest's storage. If the referenced location is not within the guest's storage, then a guest addressing exception exists. (There are no origin and limit parameters for partition 0 since a block of storage beginning at absolute address 0 is reserved for LPAR.)
The particular Dynamic Storage Reconfiguration of the ES/3090 and its successors to the present have provided a PR/SM function which allows the amount of main storage or expanded storage allocated to one or more PR/SM partitions to be changed dynamically, that is by a control program, in which DSR operations are usually initiated by the PR/SM operator and are then performed by LPAR with the assistance of the processor controller element (PCE) and the processor control program in the processor controller element.
The main storage configuration array (MSCA) is in this old machine used to translate or convert the absolute addresses used by the program running on the system to the physical addresses used to access the arrays which constitute the system's main storage. During a storage access, selected high-order bits of the absolute address were used to select an MSCA entry which, if marked valid, contained the physical array address of a block of main storage.
On machines which provide 31 bits of addressing, the MSCA is 2 times larger than the amount of main storage provided on the ES/3090 system which has been no more than 1 GB of main storage on the old and still current processors. This system operated with at least one-half of the entries in the MSCA (2 G which had to be provided for the 31 bit addressing) necessarily marked invalid before our invention. As a result, a "hole" has existed at the upper end of the absolute address space seen by the executing program. It is this hole which supports the definition of an addressing exception, and it is the exploitation of this hole and the ability of the control program to modify the contents of the MSCA in an LPAR environment which forms the basis of the old and still current DSR design.
On a system (e.g. ES/3090) with DSR installed, LPAR is able to map guest storage across the entire 2 GB host absolute address space. That is, by using appropriate origin and limit values, LPAR positions the individual guest storages in the host address space in such a way that the one large hole at the top of the host space is replaced by several smaller ones, with a smaller hole, if needed, directly above each of the guest storages. Then, with PCE assistance, LPAR manipulates the contents of the system's MSCA so as to map the guest storage into physical storage and to make the MSCA entries associated with the holes invalid.
However, when sufficient real addressing capability is not available to provide a range of holes in the host absolute addressing space without leaving some physical storage unused, storage reconfiguration can not be implemented in the old machines. Thus, when someone would actually like to have 2 G of physical memory, the prior system could not accommodate this need. The present invention solves the problems discussed above, and allows the desired advance.